S912XEQ384J3MALR Freescale Semiconductor, S912XEQ384J3MALR Datasheet - Page 582

Manufacturer Part Number

S912XEQ384J3MALR

S912XEQ Series 16 Bit 50 Mhz 384 KB Flash 24 KB Ram Microcontroller - LQFP-112

Manufacturer

Freescale Semiconductor

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description

This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not

the address sent on the bus during the address transfer.

Read and write anytime

Module Base + 0x0001

Slave Address — Bit 1 to bit 7 contain the speciﬁc slave address to be used by the IIC bus module.The default

mode of IIC bus is slave mode for an address match on the bus.

Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.

I Bus Clock Rate 7:0 — This ﬁeld is used to prescale the clock for bit rate selection. The bit clock generator is

implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and

IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown

IIC Frequency Divider Register (IBFD)

Figure 15-4. IIC Bus Frequency Divider Register (IBFD)

= Unimplemented or Reserved

MC9S12XE-Family Reference Manual Rev. 1.24

Table 15-4. I-Bus Tap and Prescale Values

Table 15-2. IBAD Field Descriptions

Table 15-3. IBFD Field Descriptions

Freescale Semiconductor