MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 106

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.10.12 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1
6.3.10.13 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0
6.3.11
By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This
register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the
system to return to Run mode, this feature is provided so that selected peripherals can be left operating in
Stop mode for the purpose of generating a wake-up interrupt.
For power-conscious applications, it is recommended that only a minimum set of peripherals be
configured to remain operational during Stop mode.
Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless
their corresponding Stop Disable control is set to 1. Refer to the 56F802x and 56F803x Peripheral
Reference Manual for further details. Reads and writes cannot be made to a module that has its clock
disabled.
Note:
6.3.11.1
6.3.11.2
106
Base + $E
RESET
•
•
•
•
•
•
•
•
Write
Read
0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled)
1 = The clock is enabled to the Timer A1 module
0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)
1 = The clock is enabled to the Timer A0 module
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
Stop Disable Register 0 (SD0)
The MSCAN module supports extended power management capabilities including Sleep,
Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. For
details, refer to the 56F802x and 56F803x Peripheral Reference Manual.
Comparator B Clock Stop Disable (CMPB_SD)—Bit 15
Comparator A Clock Stop Disable (CMPA_SD)—Bit 14
CMPB_
15
SD
0
CMPA_
SD
14
0
DAC1_
SD
13
0
Figure 6-12 Stop Disable Register 0 (SD0)
DAC0_
SD
12
0
56F8037/56F8027 Data Sheet, Rev. 7
11
0
0
ADC_
10
SD
0
9
0
0
8
0
0
7
0
0
I2C_
SD
6
0
QSCI1
_SD
5
0
QSCI0
_SD
4
0
QSPI1
_SD
Freescale Semiconductor
3
0
QSPI0
_SD
2
0
1
0
0
PWM_
SD
0
0