MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 45

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2 Interrupt Vector Table
Table 4-2
peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts
lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing
some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see
for the reset value of the VBA.
By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt
vector table. In these instances, the first two locations in the vector table must contain branch or JMP
instructions. All other entries must contain JSR instructions.
Freescale Semiconductor
Program Flash
(PFLASH)
Unified RAM (RAM)
On-Chip Memory
core
core
core
core
core
core
core
core
core
core
core
core
core
core
Peripheral
provides the 56F8037/56F8027’s reset and interrupt priority structure, including on-chip
2
3
4
5
6
7
8
9
10
11
12
13
14
Number
Vector
56F8037
32k x 16
4k x 16
64KB
8KB
3
3
3
3
1-3
1-3
1-3
1-3
1-3
2
1
0
or
or
Priority
Table 4-2 Interrupt Vector Table Contents
Level
Table 4-1 Chip Memory Configurations
56F8027
16k x 16
2k x 16
P:$00
P:$02
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
P:$10
P:$12
P:$14
P:$16
P:$18
P:$1A
32KB
Vector Base
56F8037/56F8027 Data Sheet, Rev. 7
4KB
Address +
or
or
Erase / Program via Flash interface unit and word writes to CDBW
Usable by both the Program and Data memory spaces
EOnCE Step Counter
EOnCE Breakpoint Unit
Reserved for Reset Overlay
Reserved for COP Reset Overlay
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
EOnCE Trace Buffer
EOnCE Transmit Register Empty
EOnCE Receive Register Full
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
Reserved
Interrupt Function
Use Restrictions
2
1
Interrupt Vector Table
Section 5.6.8
45