MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 31

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)
16
17
Return to
The TA2 signal is also brought out on the GPIOA4, GPIOA8 and GPIOA13 pins.
The TA3 signal is also brought out on the GPIOA5, GPIOA9 and GPIOA14 pins.
(PSRC0)
(PSRC1)
GPIOB2
(MISO0)
GPIOB3
(MOSI0)
(TA2
(TA3
Signal
Name
16
17
)
)
Table 2-2
Pin No.
LQFP
33
32
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input/
Type
Input
Input
State During
enabled
enabled
internal
internal
pull-up
pull-up
Reset
Input,
Input,
56F8037/56F8027 Data Sheet, Rev. 7
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
TA2 — Timer A, Channel 2
PSRC0 — External PWM signal source input for the complementary
PWM4/PWM5 pair.
After reset, the default state is GPIOB2. The peripheral functionality
is controlled via the SIM. See
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master Out/Slave In— This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
TA3 — Timer A, Channel 3
PSRC1 — External PWM signal source input for the complementary
PWM2/PWM3 pair.
After reset, the default state is GPIOB3. The peripheral functionality
is controlled via the SIM. See
Signal Description
Section
Section
6.3.16.
6.3.16.
56F8037/56F8027 Signal Pins
31