MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 160

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

160
SDA
SCL
1. The master mode I
2. The maximum t
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
4. A Fast mode I
5. C
Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I
Set-up time for STOP
condition
Bus free time between
STOP and START
condition
Pulse width of spikes that
must be suppressed by
the input filter
t
f
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
released.
rmax
b
S
= total capacitance of the one bus line in pF
Characteristic
+ t
SU; DAT
t
HD; STA
t
LOW
2
C bus device can be used in a Standard mode I
HD; DAT
= 1000 + 250 = 1250ns (according to the Standard mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
t
r
must be met only if the device does not stretch the LOW period (t
t
HD; DAT
Symbol
t
SU; STO
t
BUF
t
Table 10-18 I
SP
t
SU; DAT
t
HIGH
56F8037/56F8027 Data Sheet, Rev. 7
Minimum
t
f
N/A
4.0
4.7
Standard Mode
2
C Timing (Continued)
t
SU; STA
Maximum
2
C bus system, but the requirement t
N/A
—
—
SR
2
t
HD; STA
C bus specification) before the SCL line is
Minimum
0.6
1.3
0
Fast Mode
LOW
t
SP
t
SU; STO
) of the SCL signal.
Maximum
50
—
—
Freescale Semiconductor
SU; DAT
t
r
P
>= 250ns
2
Unit
t
C Bus
s
s
ns
BUF
S