MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 5

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
Part 2 Signal/Connection Descriptions . . . 19
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 44
Part 5 Interrupt Controller (ITCN) . . . . . . . . 68
Part 6 System Integration Module (SIM) . . . 93
Part 7 Security Features. . . . . . . . . . . . . . . 129
Freescale Semiconductor
1.1
1.2
1.3
1.4
1.5
1.6
2.1
2.2
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7.1
7.2
56F8037/56F8027 Features . . . . . . . . . . . 6
56F8037/56F8027 Description . . . . . . . . . 8
Award-Winning Development
Architecture Block Diagram . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . 18
Data Sheet Conventions . . . . . . . . . . . . . 18
Introduction . . . . . . . . . . . . . . . . . . . . . . . 19
56F8037/56F8027 Signal Pins . . . . . . . . 24
Overview . . . . . . . . . . . . . . . . . . . . . . . . . 40
Features . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating Modes . . . . . . . . . . . . . . . . . . 41
Internal Clock Source . . . . . . . . . . . . . . . 42
Crystal Oscillator. . . . . . . . . . . . . . . . . . . 42
Ceramic Resonator . . . . . . . . . . . . . . . . . 43
External Clock Input - Crystal Oscillator
Alternate External Clock Input . . . . . . . . 44
Introduction . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Vector Table . . . . . . . . . . . . . . . 45
Program Map . . . . . . . . . . . . . . . . . . . . . 47
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 48
EOnCE Memory Map . . . . . . . . . . . . . . . 50
Peripheral Memory-Mapped Registers . . 51
Introduction . . . . . . . . . . . . . . . . . . . . . . . 68
Features . . . . . . . . . . . . . . . . . . . . . . . . . 68
Functional Description . . . . . . . . . . . . . . 68
Block Diagram. . . . . . . . . . . . . . . . . . . . . 70
Operating Modes . . . . . . . . . . . . . . . . . . 71
Register Descriptions . . . . . . . . . . . . . . . 71
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Introduction . . . . . . . . . . . . . . . . . . . . . . . 93
Features . . . . . . . . . . . . . . . . . . . . . . . . . 94
Register Descriptions . . . . . . . . . . . . . . . 95
Clock Generation Overview . . . . . . . . . 124
Power-Saving Modes . . . . . . . . . . . . . . 124
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 126
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 129
Operation with Security Enabled. . . . . . 129
Flash Access Lock and Unlock Mechanisms130
Environment . . . . . . . . . . . . . . . . . . . 9
Option. . . . . . . . . . . . . . . . . . . . . . . 43
56F8037/56F8027 Data Sheet Table of Contents
56F8037/56F8027 Data Sheet, Rev. 7
Part 8 General Purpose Input/Output
Part 9 Joint Test Action Group (JTAG) . . .140
Part 10Specifications. . . . . . . . . . . . . . . . . .140
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .168
Part 12Design Considerations . . . . . . . . . .171
Part 13Ordering Information . . . . . . . . . . . .173
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .174
7.3
8.1
8.2
8.3
9.1
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
11.1
12.1
12.2
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .131
Product Analysis. . . . . . . . . . . . . . . . . . 131
Introduction. . . . . . . . . . . . . . . . . . . . . . 131
Configuration . . . . . . . . . . . . . . . . . . . . 131
Reset Values . . . . . . . . . . . . . . . . . . . . 135
56F8037/56F8027 Information . . . . . . . 140
General Characteristics . . . . . . . . . . . . 140
DC Electrical Characteristics . . . . . . . . 144
AC Electrical Characteristics . . . . . . . . 147
Flash Memory Characteristics . . . . . . . 148
External Clock Operation Timing . . . . . 148
Phase Locked Loop Timing . . . . . . . . . 149
Relaxation Oscillator Timing. . . . . . . . . 149
Reset, Stop, Wait, Mode Select, and
Serial Peripheral Interface (SPI) Timing 152
Quad Timer Timing. . . . . . . . . . . . . . . . 156
Queued Serial Communication Interface
Freescale’s Scalable Controller Area
Inter-Integrated Circuit Interface (I2C)
JTAG Timing. . . . . . . . . . . . . . . . . . . . . 161
Analog-to-Digital Converter (ADC)
Equivalent Circuit for ADC Inputs . . . . . 163
Comparator (CMP) Parameters . . . . . . 164
Digital-to-Analog Converter (DAC)
Power Consumption . . . . . . . . . . . . . . . 166
56F8037/56F8027 Package and
Thermal Design Considerations . . . . . . 171
Electrical Design Considerations . . . . . 172
Interrupt Timing . . . . . . . . . . . . . . 151
(QSCI) Timing . . . . . . . . . . . . . . . 158
Network (MSCAN) Timing . . . . . . 159
Timing . . . . . . . . . . . . . . . . . . . . . 159
Parameters . . . . . . . . . . . . . . . . . 162
Parameters . . . . . . . . . . . . . . . . . 164
Pin-Out Information . . . . . . . . . . . 168
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