MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 124

BOARD EVAL FOR MC56F8037

MC56F8037EVM

Manufacturer Part Number
MC56F8037EVM
Description
BOARD EVAL FOR MC56F8037
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of MC56F8037EVM

Contents
Board, Cables, CD, Debugger
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F80xx
Kit Contents
MC56F8037EVM, USB-JTAG Adapter, Cables, CD
Rohs Compliant
Yes
For Use With/related Products
MC56F8037
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC56F8037EVM
Manufacturer:
Freescale Semiconductor
Quantity:
135
6.3.23.5
This bit field is reserved. Each bit must be set to 0.
6.3.23.6
This field selects the alternate input source signal to feed Quad Timer A, input 1.
6.3.23.7
This bit field is reserved. Each bit must be set to 0.
For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A
module must be identical, at either the system clock rate or 3X system clock rate.
6.4 Clock Generation Overview
The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to
produce a system clock at a maximum of 32MHz for the peripheral, core and memory. It divides the master
clock by two and gates it with appropriate power mode and clock gating controls. A 3X system high-speed
peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and
can be an optional clock for PWM, Timer A, Timer B, and I
gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can be selected as the master
clock source (MSTR_OSC). An external clock can be operated at any frequency up to 64MHz. The crystal
oscillator can be operated only at a maximum of 8MHz. The relaxation oscillator can be operated at full
speed (8MHz), standby speed (200kHz using ROSB), or powered down (using ROPD). An 8MHz
MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high-speed
clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master
clocks to the SIM. When the PLL is selected, both the 3X system clock and the 2X system clock are
enabled. If the PLL is not selected, the 3X system clock is disabled and the master clock is MSTR_OSC.
In combination with the OCCS module, the SIM provides power modes (see
and clock rate controls to provide flexible control of clocking and power utilization. The clock rate
controls enable the high-speed clocking option for the two quad timers (TMRA and TMRB) and PWM,
but requires the PLL to be on and selected. Refer to the 56F802x and 56F803x Peripheral Reference
Manual for further details. The peripheral clock enable controls can be used to disable an individual
peripheral clock when it is not used.
6.5 Power-Saving Modes
The 56F8037/56F8027 operates in one of five Power-Saving modes, as shown in
124
0 = I/O pin (External) - Use Timer A1 input/output pin
1 = CMPAO (Internal) - Use Comparator A output
Reserved—Bits 7–5
Select Peripheral Input Source for TA1 (IPS2_TA1)—Bit 4
Reserved—Bits 3–0
56F8037/56F8027 Data Sheet, Rev. 7
2
C modules. These clocks are generated by
Section
Table 6-2
Freescale Semiconductor
6.5), clock enables,
.

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