MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 4

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

56F8037/56F8027 General Description
4
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
• 56F8037 offers 64KB (32K x 16) Program Flash
• 56F8027 offers 32KB (16K x 16) Program Flash
• 56F8037 offers 8KB (4K x 16) Unified Data/Program
• 56F8027 offers 4KB (2K x 16) Unified Data/Program
• One 6-channel PWM module
• Two 8-channel 12-bit Analog-to-Digital Converters
• Two 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
C-efficient architecture
RAM
RAM
(ADCs)
14
2
8
8
Programmable
AD0
AD1
or GPIOD
Interval
or GPIOC
or QSCI1
Timer
DAC
or CMP
ADC
or GPIOB
or TMRB
or CAN
or CMP
I
2
C
6
or TMRA or TMRB
or CMP or QSPI1
or GPIOA
PWM
or GPIOB
or TMRA
or PWM
QSPI0
or I
4
2
C
Program Memory
32K x 16 Flash
16K x 16 Flash
Program RAM
Unified Data /
Memory
4K x 16
2K x 16
or GPIOB
or QSPI1
or TMRA
or TMRB
or PWM
56F8037/56F8027 Block Diagram
QSCI0
or I
2
IPBus Bridge (IPBB)
4
C
56F8037/56F8027 Data Sheet, Rev. 7
Program Controller
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
and Hardware
Watchdog
RESET or
Looping Unit
GPIOA
COP/
PAB
CDBR
CDBW
PDB
JTAG/EOnCE
Controller
Interrupt
Generation Unit
Port or
GPIOD
4
Address
• Three Programmable Interval Timers (PITs)
• Two Queued Serial Communication Interfaces (QSCIs)
• Two Queued Serial Peripheral Interfaces (QSPIs)
• Freescale’s scalable controller area network (MSCAN)
• Two 16-bit Quad Timers
• One Inter-Integrated Circuit (I
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
with LIN slave functionality
2.0 A/B Module
Interrupt (LVI) module
unobtrusive, real-time debugging
56800E Core
V
2
16-Bit
Integration
CAP
Three 16-bit Input Registers
System
Module
System Bus
16 x 16 + 36 -> 36-Bit MAC
Four 36-bit Accumulators
3
V
Control
DD
Digital Reg
Data ALU
P
O
R
4
V
Low-Voltage
SS
Supervisor
R/W Control
Relaxation Oscillator
Generator*
*Includes On-Chip
V
Clock
Analog Reg
DDA
V
Manipulation
SSA
O
C
S
Unit
Bit
Freescale Semiconductor
2
C) port
EXTAL or GPIOD
XTAL, CLKIN, or
GPIOD