MC56F8037EVM Freescale Semiconductor, MC56F8037EVM Datasheet - Page 97

• Manufacturer Part Number: MC56F8037EVM
• Description: BOARD EVAL FOR MC56F8037
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of MC56F8037EVM

• Contents: Board, Cables, CD, Debugger
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F80xx
• Kit Contents: MC56F8037EVM, USB-JTAG Adapter, Cables, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.1
6.3.1.1
This bit field is reserved. Each bit must be set to 0.
6.3.1.2
Note:
6.3.1.3
6.3.1.4
6.3.1.5
Freescale Semiconductor
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0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Writing 1 to this field will cause the device to reset
Read is zero
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
RESET
Write
Read
SIM_IPS2
Reserved
SIM Control Register (SIM_CTRL)
Using default state “0” is recommended.
write-protected until the next reset
write-protected until the next reset
STOP_DISABLE field is write-protected until the next reset
WAIT_DISABLE field is write-protected until the next reset
Reserved—Bits 15–6
OnCE Enable (ONCEEBL)—Bit 5
Software Reset (SWRST)—Bit 4
Stop Disable (STOP_DISABLE)—Bits 3–2
Wait Disable (WAIT_DISABLE)—Bits 1–0
W
R
15
0
0
0
0
14
0
0
= Read as 0
Figure 6-2 SIM Control Register (SIM_CTRL)
0
13
Figure 6-1 SIM Register Map Summary
0
0
0
12
0
0
56F8037/56F8027 Data Sheet, Rev. 7
IPS2_
TA3
11
0
0
0
1
10
0
0
=
Read as 1
0
9
0
0
0
8
0
0
IPS2_
TA2
7
0
0
0
6
0
0
= Reserved
0
ONCE
EBL
5
0
0
RST
SW
4
0
IPS2_
TA1
3
DISABLE
0
STOP_
0
2
0
Register Descriptions
0
1
DISABLE
0
WAIT_
0
0
0
0
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