DV164136 Microchip Technology, DV164136 Datasheet - Page 350

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
MULLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39646C-page 348
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
PRODH
PRODL
W
PRODH
PRODL
Q1
literal ‘k’
Multiply Literal with W
MULLW
0 ≤ k ≤ 255
(W) x k → PRODH:PRODL
None
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
1
1
MULLW
Read
0000
Q2
=
=
=
=
=
=
E2h
?
?
E2h
ADh
08h
k
0C4h
1101
Process
Data
Q3
kkkk
PRODH:
registers
PRODL
Write
Q4
kkkk
MULWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
PRODH
PRODL
W
REG
PRODH
PRODL
Q1
Multiply W with f
MULWF
0 ≤ f ≤ 255
a ∈ [0,1]
(W) x (f) → PRODH:PRODL
None
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
register ‘f’
0000
MULWF
Read
Q2
=
=
=
=
=
=
=
=
© 2008 Microchip Technology Inc.
f {,a}
C4h
B5h
?
?
C4h
B5h
8Ah
94h
001a
REG, 1
Process
Data
Q3
ffff
registers
PRODH:
PRODL
Write
Q4
ffff