DV164136 Microchip Technology, DV164136 Datasheet - Page 259

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.2
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be used
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTAx<2> and BAUDCONx<3>).
Parity is not supported by the hardware, but can be
implemented in software and stored as the 9th data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
20.2.1
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSRx). The Shift register
obtains its data from the Read/Write Transmit Buffer
register, TXREGx. The TXREGx register is loaded with
data in software. The TSRx register is not loaded until
the Stop bit has been transmitted from the previous
load. As soon as the Stop bit is transmitted, the TSRx
is loaded with new data from the TXREGx register (if
available).
© 2008 Microchip Technology Inc.
EUSART Asynchronous Mode
EUSART ASYNCHRONOUS
TRANSMITTER
Once the TXREGx register transfers the data to the
TSRx register (occurs in one T
is empty and the TXxIF flag bit (PIR1<4>) is set. This
interrupt can be enabled or disabled by setting or clearing
the interrupt enable bit, TXxIE (PIE1<4>). TXxIF will be
set regardless of the state of TXxIE; it cannot be cleared
in software. TXxIF is also not cleared immediately upon
loading TXREGx, but becomes valid in the second
instruction cycle following the load instruction. Polling
TXxIF immediately following a load of TXREGx will return
invalid results.
While TXxIF indicates the status of the TXREGx regis-
ter, another bit, TRMT (TXSTAx<1>), shows the status
of the TSRx register. TRMT is a read-only bit which is
set when the TSRx register is empty. No interrupt logic
is tied to this bit so the user has to poll this bit in order
to determine if the TSRx register is empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
PIC18F8722 FAMILY
Note 1: The TSRx register is not mapped in data
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
Enable the transmission by setting bit, TXEN,
which will also set bit, TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREGx register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2: Flag bit, TXxIF, is set when enable bit
memory so it is not available to the user.
TXEN is set.
CY
), the TXREGx register
DS39646C-page 257