DV164136 Microchip Technology, DV164136 Datasheet - Page 219
DV164136
Manufacturer Part Number
DV164136
Description
DEVELOPMENT KIT FOR PIC18
Manufacturer
Microchip Technology
Series
PIC®r
Type
MCUr
Datasheets
1.DM183032.pdf
(38 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(6 pages)
4.DV164136.pdf
(446 pages)
5.DV164136.pdf
(4 pages)
6.DV164136.pdf
(18 pages)
Specifications of DV164136
Contents
Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
Processor To Be Evaluated
PIC18F8722, PIC18F87J11
Interface Type
RS-232, USB
Operating Supply Voltage
3.3 V, 5 V
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18F8xxx
Kit Contents
PIC18 Exp Brd PICkit 3 Cable CD PSU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PIC18F8722, PIC18F87J11
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DV164136
Manufacturer:
MICROCHIP
Quantity:
12 000
- DM183032 PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- DV164136 PDF datasheet #4
- DV164136 PDF datasheet #5
- DV164136 PDF datasheet #6
- Current page: 219 of 446
- Download datasheet (7Mb)
REGISTER 19-4:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WCOL
R/W-0
When enabled, the SDAx and SCLx pins must be configured as input.
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: SCKx Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
SSPOV
R/W-0
transmission to be started (must be cleared in software)
software)
in software)
SSPxCON1: MSSPx CONTROL REGISTER 1 (I
2
2
2
2
2
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Firmware Controlled Master mode (Slave Idle)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
(1)
R/W-0
CKP
OSC
/(4 * (SSPxADD + 1))
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
SSPM3
R/W-0
PIC18F8722 FAMILY
SSPM2
2
R/W-0
C™ MODE)
2
C™ conditions were not valid for a
x = Bit is unknown
SSPM1
R/W-0
DS39646C-page 217
SSPM0
R/W-0
bit 0
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