DV164136 Microchip Technology, DV164136 Datasheet - Page 195

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 18-1:
18.4.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the equation:
EQUATION 18-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
TABLE 18-4:
© 2008 Microchip Technology Inc.
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle =
PWM Frequency
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
CCPR1H (Slave)
Duty Cycle Registers
PWM DUTY CYCLE
Comparator
CCPR1L
PR2
TMR2
Comparator
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
(CCPR1L:CCP1CON<5:4>) •
T
OSC
(Note 1)
Clear Timer,
set ECCP1 pin and
latch D.C.
• (TMR2 Prescale Value)
CCP1CON<5:4>
2.44 kHz
FFh
16
10
R
S
P1M1<1:0>
9.77 kHz
Q
FFh
10
4
ECCP1DEL
Controller
ECCP1/P1A
Output
39.06 kHz
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 18-3:
2
PIC18F8722 FAMILY
Note:
FFh
10
1
P1B
P1C
P1D
PWM Resolution (max) =
CCP1M<3:0>
4
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
156.25 kHz
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
3Fh
1
8
312.50 kHz
1Fh
log
1
7
(
log(2)
ECCP1/P1A
P1B
P1C
P1D
DS39646C-page 193
F
F
PWM
OSC
)
416.67 kHz
bits
6.58
17h
1