DV164136 Microchip Technology, DV164136 Datasheet - Page 210

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
19.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP module consists of a transmit/receive shift
register (SSPxSR) and a buffer register (SSPxBUF).
The SSPxSR shifts the data in and out of the device,
MSb first. The SSPxBUF holds the data that was
written to the SSPxSR until the received data is ready.
Once the 8 bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
detect bit, BF (SSPxSTAT<0>) and the interrupt flag bit,
SSPxIF, are set. This double-buffering of the received
data (SSPxBUF) allows the next byte to start reception
EXAMPLE 19-1:
DS39646C-page 208
LOOP
output time)
SCKx)
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
OPERATION
SSP1STAT, BF
LOOP
SSP1BUF, W
RXDATA
TXDATA, W
SSP1BUF
LOADING THE SSP1BUF (SSP1SR) REGISTER
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
before reading the data that was just received. Any
write to the SSPxBUF register during transmis-
sion/reception of data will be ignored and the Write
Collision Detect bit, WCOL (SSPxCON1<7>), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPxBUF register completed successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is
read, the BF bit is cleared. This data may be irrelevant
if the SPI is only a transmitter. Generally, the MSSP
interrupt is used to determine when the transmis-
sion/reception has completed. If the interrupt method is
not going to be used, then software polling can be done
to ensure that a write collision does not occur.
Example 19-1 shows the loading of the SSPxBUF
(SSPxSR) for data transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
© 2008 Microchip Technology Inc.