C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 150

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
150
Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1).
Bit 3:
Bit 2:
Bits 1–0: CHMSTH: Cache Miss Penalty Threshold.
SFR Page:
SFR Address:
R/W
Bit7
These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first
be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition
14.4).
CHALGM: Cache Algorithm Select.
This bit selects the cache replacement algorithm.
0: Cache uses Rebound algorithm.
1: Cache uses Pseudo-random algorithm.
CHFIXM: Cache Fix MOVC Enable.
This bit forces MOVC writes to the cache memory to use slot 0.
0: MOVC data is written according to the current algorithm selected by the CHALGM bit.
1: MOVC data is always written to cache slot 0.
These bits determine when missed instruction data will be cached.
If data takes longer than CHMSTH clocks to obtain, it will be cached.
F
0xC9
R/W
Bit6
CHMSCTL
SFR Definition 14.2. CCH0TN: Cache Tuning
R/W
Bit5
R/W
Bit4
CHALGM CHFIXM
Rev. 1.0
R/W
Bit3
R/W
Bit2
R/W
Bit1
CHMSTH
R/W
Bit0
00000100
Reset Value