C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 156

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

C8051F360/1/2/3/4/5/6/7/8/9
156
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bit 4:
Bits 3–2: EMD1–0: EMIF Operating Mode Select.
Bits 1–0: EALE1–0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
SFR Page:
SFR Address:
R/W
Bit7
–
EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
01: Split Mode without Bank Select: Accesses below the 1 k boundary are directed on-chip.
10: Split Mode with Bank Select: Accesses below the 1 k boundary are directed on-chip.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
F
0xC7
SFR Definition 15.2. EMI0CF: External Memory Configuration
on-chip memory space.
Accesses above the 1 k boundary are directed off-chip. 8-bit off-chip MOVX operations
use the current contents of the Address High port latches to resolve upper address byte.
Note that in order to access off-chip space, EMI0CN must be set to a page that is not
contained in the on-chip address space.
Accesses above the 1 k boundary are directed off-chip. 8-bit off-chip MOVX operations
use the contents of EMI0CN to determine the high-byte of the address.
CPU.
R/W
Bit6
–
R/W
Bit5
–
EMD2
R/W
Bit4
Rev. 1.0
EMD1
R/W
Bit3
EMD0
R/W
Bit2
EALE1
R/W
Bit1
EALE0
R/W
Bit0
00000011
Reset Value