C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 186

KIT DEV FOR C8051F360 FAMILY

C8051F360DK

Manufacturer Part Number
C8051F360DK
Description
KIT DEV FOR C8051F360 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F360DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F36x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1410
C8051F360/1/2/3/4/5/6/7/8/9
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.1
(C8051F360/3) or P0.4 (C8051F361/2/4/5/6/7/8/9); UART RX0 is always assigned to P0.2 (C8051F360/3)
or P0.5 (C8051F361/2/4/5/6/7/8/9). Standard Port I/Os appear contiguously starting at P0.0 after prioritized
functions and skipped pins are assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
186
(32- and 28-
PIN I/O
TX0
RX0
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
SF Signals
SF Signals
(48-pin)
pin)
Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped
0
0
1
0
2
0
P0SKIP[0:7]
3
0
P0
4
0
5
0
6
0
7
0
0
1
1
1
2
0
P1SKIP[0:7]
3
0
P1
4
0
Rev. 1.0
5
0
6
0
7
0
(32-pin and 28-pin packages)
(48-pin package)
(*4-Wire SPI Only)
0
0
1
0
2
0
P2SKIP[0:7]
3
0
P2
4
0
5
0
6
0
7
0
0
0
32/48-pin only
available on
1
0
P3.1-P3.4
2
0
P3SKIP[0:7]
3
0
P3
4
0
available
P3.5-P3.7
on 48-pin
5
0
only
6
0
7
0

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