C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 277

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3–1: CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
Bit 0:
Note:When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the contents of the
SFR Page:
SFR Address:
CIDL
R/W
Bit7
PCA0MD register, the Watchdog Timer must first be disabled.
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 5 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 5 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
UNUSED. Read = 0b, Write = don't care.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Note: External clock divided by 8 is synchronized with the system clock.
all pages
0xD9
CPS2
WDTE
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
0
0
1
1
0
0
1
1
SFR Definition 22.2. PCA0MD: PCA0 Mode
WDLCK
R/W
Bit5
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8 (synchronized with system clock)
Reserved
Reserved
–
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
CPS2
R/W
Bit3
CPS1
R/W
Bit2
Timebase
CPS0
R/W
Bit1
ECF
R/W
Bit0
01000000
Reset Value
277