C8051F360DK Silicon Laboratories Inc, C8051F360DK Datasheet - Page 151

• Manufacturer Part Number: C8051F360DK
• Description: KIT DEV FOR C8051F360 FAMILY
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F360DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F36x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F360, F361, F362, F363, F364, F365, F366, F367, F368, F369
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1410

Bit 7:
Bit 6:
Bit 5:
Bits 4–0: CHSLOT: Cache Slot Pointer.
SFR Page:
SFR Address:
CHPUSH
R/W
Bit7
CHPUSH: Cache Push Enable.
This bit enables cache push operations, which will lock information in cache slots using
MOVC instructions.
0: Cache push operations are disabled.
1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-
Note:No more than 30 cache slots should be locked at one time, since the entire cache will be unlocked
when CHSLOT is equal to 0.
CHPOP: Cache Pop.
Writing a ‘1’ to this bit will increment CHSLOT and then unlock that location. This bit always
reads ‘0’. Note that Cache Pop operations should not be performed while CHSLOT =
11110b. “Pop”ing more Cache slots than have been “Push”ed will have indeterminate results
on the Cache performance.
RESERVED. Read = 0b. Must Write 0b.
These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are
locked, and will not be changed by the processor, except when CHSLOT equals 0.
F
0xD2
byte segment containing the data is locked into the cache at the location indicated by
CHSLOT, and CHSLOT is decremented.
CHPOP RESERVED
R/W
Bit6
SFR Definition 14.3. CCH0LC: Cache Lock Control
Bit5
R
Bit4
R
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
Bit3
R
CHSLOT
Bit2
R
Bit1
R
Bit0
R
Reset Value
00011111
151