EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 38

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADuC832
MODE 4: Dual NRZ 16-Bit - DAC
Mode 4 provides a high speed PWM output similar to that of a
clock equal to 16.777216 MHz.
In this mode P2.6 and P2.7 are updated every PWM clock
(60 ns in the case of 16 MHz). Over any 65536 cycles (16-bit
PWM) PWM0 (P2.6) is high for PWM0H/L cycles and low for
(65536 – PWM0H/L) cycles. Similarly PWM1 (P2.7) is high for
PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
For example, if PWM1H was set to 4010H (slightly above one
quarter of FS) then typically P2.7 will be low for three clocks
and high for one clock (each clock is approximately 60 ns). Over
every 65536 clocks, the PWM will compensate for the fact that
the output should be slightly above one quarter of full scale by
having a high cycle followed by only two low cycles.
For faster DAC outputs (at lower resolution) write 0s to the
LSBs that are not required. If for example only 12 bit perfor-
mance is required then write 0s to the four LSBs. This means
that a 12-bit accurate S-D DAC output can occur at 4.096 kHz.
Similarly writing 0s to the eight LSBs gives an 8-bit accurate
S-D DAC output at 65 kHz.
MODE 5: Dual 8-Bit PWM
In Mode 5, the duty cycle of the PWM outputs and the resolution
of the PWM outputs are individually programmable. The maxi-
mum resolution of the PWM output is eight bits. The output
resolution is set by the PWM1L and PWM1H SFRs for the
P2.6 and P2.7 outputs, respectively. PWM0L and PWM0H sets
the duty cycles of the PWM outputs at P2.6 and P2.7, respectively.
Both PWMs have same clock source and clock divider.
- DAC. Typically, this mode will be used with the PWM
16.777MHz
PWM0H/L = C000H
PWM1H/L = 4000H
16-BIT
16-BIT
16-BIT
16-BIT
Figure 30. PWM Mode 4
LATCH
CARRY OUT AT P1.0
CARRY OUT AT P2.7
16-BIT
16-BIT
60 s
60 s
0
0
1
0
1
0
1
1
0
0
0
1
1
0
–38–
MODE 6: Dual RZ 16-Bit - DAC
Mode 6 provides a high speed PWM output similar to that of a
the key difference is that Mode 6 provides return-to-zero (RZ)
DAC outputs. The RZ mode ensures that any difference in the
rise and fall times will not effect the - DAC INL. However,
the RZ mode halves the dynamic range of the - DAC outputs
from 0–AV
should be used with a PWM clock divider of four.
If PWM1H was set to 4010H (slightly above one quarter of FS)
then typically P2.7 will be low for three full clocks (3
high for half a clock (30 ns), and then low again for half a clock
(30 ns) before repeating itself. Over every 65536 clocks the PWM
will compensate for the fact that the output should be slightly
above one quarter of full scale by leaving the output high for
two half clocks in four every so often.
- DAC. Mode 6 operates very similarly to Mode 4. However,
- DAC output. Mode 4 provides non-return-to-zero -
PWM0H/L = C000H
PWM1H/L = 4000H
4MHz
16-BIT
16-BIT
0, 3/4, 1/2, 1/4, 0
16-BIT
16-BIT
DD
down to 0–AV
Figure 31. PWM Mode 5
Figure 32. PWM Mode 6
LATCH
PWM COUNTERS
CARRY OUT AT P2.6
CARRY OUT AT P2.7
DD
/2. For best results, this mode
16-BIT
16-BIT
240 s
240 s
0 1
0
0
1
0 1
1
0
P2.6
PWM1H
PWM0H
P2.7
PWM1L
PWM0L
0
0
60 ns),
1
REV. 0
0
1
0