EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 63

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

Separate analog and digital power supply pins (AV
respectively) allow AV
signals often present on the system DV
you can power AV
desired, you must ensure that they remain within ± 0.3 V of one
another at all times in order to avoid damaging the chip (as per
the Absolute Maximum Ratings section). Therefore, it is recom-
mended that unless AV
together, you connect back-to-back Schottky diodes between
them as shown in Figure 60.
As an alternative to providing two separate power supplies, the
user can help keep AV
and/or ferrite bead between it and DV
AV
shown in Figure 61. With this configuration other analog circuitry
(such as op amps, voltage reference, and so on) can be powered
from the AV
include back-to-back Schottky diodes between AV
order to protect from power-up and power-down transient condi-
tions that could separate the two supply voltages momentarily.
Notice that in both Figure 60 and Figure 61, a large value (10 mF)
reservoir capacitor sits on DV
sits on AV
located at each V
tice, be sure to include all of these capacitors, and ensure the
smaller capacitors are close to each AV
as short as possible. Connect the ground terminal of each of
these capacitors directly to the underlying ground plane. Finally,
REV. 0
DD
Figure 61. External Single-Supply Connections
separately to ground. An example of this configuration is
Figure 60. External Dual-Supply Connections
DIGITAL SUPPLY
0.1 F
DD
0.1 F
+
–
DD
+
–
. Also, local small-value (0.1 mF) capacitors are
DIGITAL SUPPLY
supply line as well. The user will still want to
DD
DD
10 F
pin of the chip. As per standard design prac-
DD
and DV
DD
10 F
DD
to be kept relatively free of noisy digital
quiet by placing a small series resistor
and DV
DV
DGND
DD
DV
DGND
DD
BEAD
DD
DD
ADuC832
ADuC832
from two separate supplies if
and a separate 10 mF capacitor
DD
are connected directly
DD
DD
1.6
DD
AGND
AGND
AV
AV
, and then decoupling
line. However, though
ANALOG SUPPLY
DD
pin with trace lengths
10 F
DD
10 F
DD
0.1 F
0.1 F
DD
and DV
and DV
+
–
DD
DD
in
,
–63–
it should also be noted that, at all times, the analog and digital
ground pins on the ADuC832 must be referenced to the same
system ground reference point.
Power Consumption
The currents consumed by the various sections of the ADuC832
are shown in Table XXXIV. The Core values given represent the
current drawn by DV
are pulled by the AV
when not in use. The other on-chip peripherals (watchdog timer,
power supply monitor, and so on) consume negligible current
and are therefore lumped in with the Core operating current here.
Of course, the user must add any currents sourced by the parallel
and serial I/O pins, and sourced by the DAC, in order to deter-
mine the total current needed at the ADuC832’s supply pins.
Also, current drawn from the DV
approximately 10 mA during Flash/EE erase and program cycles.
Core:
Core:
ADC:
DAC (Each):
Voltage Ref:
Since operating DV
speed, the expressions for Core supply current in Table XXXIV
are given as functions of M
a value for M
the core at that oscillator frequency. Since the ADC and DACs
can be enabled or disabled in software, add only the currents
from the peripherals you expect to use. And again, do not forget
to include current sourced by I/O pins, serial port pins, DAC
outputs, and so forth, plus the additional current drawn during
Flash/EE erase and program cycles.
A software switch allows the chip to be switched from normal
mode into idle mode, and also into full power-down mode.
Below are brief descriptions of power-down and idle modes.
Power Saving Modes
In idle mode, the oscillator continues to run but the core clock
generated from the PLL is halted. The on-chip peripherals
continue to receive the clock, and remain functional. The CPU
status is preserved with the stack pointer and program counter,
and all other internal registers maintain their data during idle
mode. Port pins and DAC output pins retain their states in this
mode. The chip will recover from idle mode upon receiving any
enabled interrupt, or upon receiving a hardware reset.
In full power-down mode, both the PLL and the clock to the core
are stopped. The on-chip oscillator can be halted or can continue
to oscillate depending on the state of the oscillator power-down
bit in the PLLCON SFR. The TIC, being driven directly from
(Normal Mode) (1.6 nAs
(Idle Mode)
Table XXXIV. Typical I
CLK
in hertz to determine the current consumed by
V
6 mA
(0.75 nAs
5 mA
1.3 mA
250 mA
200 mA
DD
DD
DD
DD
current is primarily a function of clock
, while the rest (ADC, DAC, voltage ref)
pin and can be disabled in software
= 5 V
CLK
M
, the core clock frequency. Plug in
DD
M
CLK
CLK
DD
of Core and Peripherals
) +
) +
supply will increase by
V
(0.8 nAs
3 mA
(0.25 nAs
3 mA
1.0 mA
200 mA
150 mA
DD
ADuC832
= 3 V
M
M
CLK
CLK
) +
) +