EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 40

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADuC832
SPIDAT
Function
SFR Address
Power-On Default Value
Bit Addressable
Using the SPI Interface
Depending on the configuration of the bits in the SPICON SFR
shown in Table XIII, the ADuC832 SPI interface will transmit
or receive data in a number of possible modes. Figure 33 shows
all possible ADuC832 SPI configurations and the timing rela-
tionships and synchronization between the signals involved.
Also shown in this figure is the SPI interrupt bit (ISPI) and how
it is triggered at the end of each byte-wide communication.
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
DATA OUTPUT
SAMPLE INPUT
DATA OUTPUT
Figure 33. SPI Timing, All Modes
(CPOL = 1)
(CPOL = 0)
ISPI FLAG
ISPI FLAG
SCLOCK
SCLOCK
SS
?
MSB BIT 6 BIT 5
SPI Data Register
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to
read data just received by the SPI interface.
F7H
00H
No
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
–40–
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and gener-
ates a burst of eight clocks whenever user code writes to the
SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the
SS pin is not used in master mode. If the ADuC832 needs to
assert the SS pin on an external slave device, a port digital output
pin should be used.
In master mode, a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period a data bit is also sampled via MISO.
After eight clocks, the transmitted byte will have been completely
transmitted and the input byte will be waiting in the input shift
register. The ISPI flag will be set automatically and an interrupt
will occur if enabled. The value in the shift register will be latched
into SPIDAT.
SPI Interface—Slave Mode
In slave mode the SCLOCK is an input. The SS pin must
also be driven low externally during the byte communication.
Transmission is also initiated by a write to SPIDAT. In slave
mode, a data bit is transmitted via MISO and a data bit is received
via MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and the
input byte will be waiting in the input shift register. The ISPI flag
will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT only
when the transmission/reception of a byte has been completed.
The end of transmission occurs after the eighth clock has been
received if CPHA = 1, or when SS returns high if CPHA = 0.
REV. 0