EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADuC832
Parameter
POWER REQUIREMENTS
NOTES
10
11
12
13
14
15
16
17
18
19
20
Specifications subject to change without notice.
SPECIFICATIONS
1
2
3
4
5
6
7
8
9
Temperature Range –40ºC to +125ºC.
ADC linearity is guaranteed during normal MicroConverter core operation.
ADC LSB Size = V
These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these
specifications.
SNR calculation includes distortion and noise components.
Channel-to-channel crosstalk is measured on adjacent channels.
The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.
unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
decoupling capacitor chosen for both the V
pins need to be shorted together for correct operation.
will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section.
DAC linearity is calculated using:
DAC differential nonlinearity specified on 0 to V
DAC specification for output impedance in the unbuffered case depends on DAC code.
DAC specifications for I
Measured with V
When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the V
Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40ºC, +25ºC, and +125ºC. Typical endurance at 25ºC is 700,000 cycles.
Retention lifetime equivalent at junction temperature (T
Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
DV
Power Supply Voltages
Power Supply Currents Normal Mode
Power Supply Currents Idle Mode
Power Supply Currents Power-Down Mode
Typical Additional Power Supply Currents
Reduced code range of 100 to 4095, 0 to V
Reduced code range of 100 to 3945, 0 to V
DAC Output Load = 10 kΩ and 100 pF.
Normal Mode:
Idle Mode:
Power-Down Mode:
DD
AV
DV
AV
DV
AV
DV
AV
DV
AV
DV
AV
DV
PSM Peripheral
ADC
DAC
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
/DV
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
DD
REF
REF
– AGND
and C
4
4
4
/2
SINK
12
i.e., for Internal V
REF
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in
idle mode.
Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON,
PCON.0 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR
, voltage output settling time and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in
pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference will be determined by the value of the
(continued)
19, 20
REF
REF
REF
DD
and C
= 2.5 V, 1 LSB = 610 µV and for External V
range.
REF
range.
REF
and 0 to V
J
pins.
) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV
V
4.5
5.5
6
1.7
23
20
1.7
4
0.14
10
9
0.14
80
38
2
35
25
50
1.5
150
DD
= 5 V
DD
ranges.
V
2.7
3.3
3
1.7
12
10
1.7
2
0.14
5
4
0.14
25
14
1
20
12
–6–
DD
= 3 V
REF
= 1 V, 1 LSB = 244 µV.
Unit
V min
V max
V min
V max
mA max
mA max
mA max
mA typ
mA max
mA typ
mA typ
mA max
mA typ
mA typ
µA max
µA typ
µA typ
µA max
µA typ
µA typ
mA typ
µA typ
Test Conditions/Comments
AV
AV
Core CLK = 2.097 MHz
Core CLK = 2.097 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 2.097 MHz
Core CLK = 2.097 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 2.097 MHz or 16.78 MHz
Osc. On
Osc. Off
AV
DD
DD
DD
/DV
/DV
= DV
DD
DD
DD
= 3 V nom
= 5 V nom
= 5 V
REF
and C
REV. 0
REF