EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 45

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

WDCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
REV. 0
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC832
enters an erroneous state, possibly due to a programming error or
electrical noise. The watchdog function can be disabled by clearing
the WDE (Watchdog Enable) bit in the Watchdog Control
(WDCON) SFR. When enabled, the watchdog circuit will gener-
ate a system reset or interrupt (WDS) if the user program fails
to set the watchdog (WDE) bit within a predetermined amount
Name
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
Watchdog Timer Control Register
Description
Watchdog Timer Prescale Bits.
The Watchdog timeout period is given by the equation: t
(0 ≤ PRE ≤ 7; f
PRE3 PRE2 PRE1 PRE0
0
0
0
0
0
0
0
0
1
PRE3–0 > 1000
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog will generate an interrupt response instead of a system
reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR
EA instruction and it is also a fixed, high priority interrupt. If the watchdog is not being used to
monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout
period in which an interrupt will be generated.
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If this bit is not set by the user
within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending
on WDIR. Cleared under the following conditions: User writes “0,” Watchdog Reset
(WDIR = “0”); Hardware Reset; PSM Interrupt.
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit
must be set and the very next instruction must be a write instruction to the WDCON SFR.
For example:
C0H
10H
Yes
0
0
0
0
1
1
1
1
0
CLR
SETB WDWR
MOV
SETB EA
Table XVI. WDCON SFR Bit Designations
0
0
1
1
0
0
1
1
0
EA
WDCON, #72H ;enable WDT for 2.0s timeout
XTAL
= 32.768 kHz)
0
1
0
1
0
1
0
1
0
–45–
Timeout Period (ms) Action
15.6
31.2
62.5
125
250
500
1000
2000
0.0
;disable interrupts while writing
;allow write to WDCON
;enable interrupts again (if rqd)
;to WDT
of time (see PRE3–0 bits in WDCON). The watchdog timer itself
is a 16-bit counter that is clocked directly from the 32.768 kHz
external crystal. The watchdog time out interval can be adjusted
via the PRE3–0 bits in WDCON. Full control and status of the
watchdog timer function can be controlled via the watchdog timer
control SFR (WDCON). The WDCON SFR can only be written
by user software if the double write sequence described in WDWR
below is initiated on every write access to the WDCON SFR.
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
WD
= (2
PRE
(2
9
/f
ADuC832
XTAL
))