EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 73
EVAL-ADUC832QSZ
Manufacturer Part Number
EVAL-ADUC832QSZ
Description
KIT DEV FOR ADUC832 QUICK START
Manufacturer
Analog Devices Inc
Series
QuickStart™ Kitr
Type
MCUr
Specifications of EVAL-ADUC832QSZ
Contents
Evaluation Board, Cable, Power Supply, Software and Documentation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADuC832
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
EVAL-ADUC832QS
EVAL-ADUC832QS
EVAL-ADUC832QS
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Parameter
SPI MASTER MODE TIMING (CPHA = 1)
t
t
t
t
t
t
t
t
t
*Characterized under the following conditions:
REV. 0
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 2.09 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
SCLOCK Low Pulsewidth*
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
MOSI
MISO
t
Figure 75. SPI Master Mode Timing (CPHA = 1)
DAV
t
SH
t
DSU
MSB IN
t
DHD
MSB
t
SL
t
DF
–73–
t
DR
Min
100
100
BIT 6 – 1
BIT 6 – 1
t
SR
Typ
476
476
10
10
10
10
t
SF
LSB IN
Max
50
25
25
25
25
LSB
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC832
Figure
75
75
75
75
75
75
75
75
75
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