MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 10
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10
Mnemonic
OSCAUD
OSC24M
IOMUX
Block
IPUv1
I
2
KPP
IIM
C(3)
I
IC
identification
module
External
signals and pin
multiplexing
Image
processing unit
Keypin port
OSC audio
reference
oscillator
OSC24M
24-MHz
reference
oscillator
2
Block Name
C module
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
ARM
ARM
ARM
ARM
ARM
Analog
Analog
Domain
Table 4. Digital and Analog Modules (continued)
1
ARM1136
platform
peripherals
Security
modules
Pins
Multimedia
peripherals
Connectivity
peripherals
Clock
Clock
Subsystem
Inter-integrated circuit (I
serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. I
applications requiring occasional communications over a short
distance among many devices. The interface operates at up to
100 kbps with maximum bus loading and timing. The I
a true multiple-master bus, with arbitration and collision detection
that prevent data corruption if multiple devices attempt to control the
bus simultaneously. This feature supports complex applications with
multiprocessor control and can be used for rapid testing and
alignment of end products through external connections to an
assembly-line computer.
The IIM provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys,
and various control signals requiring a fixed value.
Each I/O multiplexer provides a flexible, scalable multiplexing
solution with the following features:
The IPU supports video and graphics processing functions. It also
provides the interface for image sensors and displays. The IPU
performs the following main functions:
Can be used for either keypin matrix scanning or general purpose
I/O.
The OSCAUDIO oscillator provides a stable frequency reference for
the PLLs. This oscillator is designed to work in conjunction with an
external 24.576-MHz crystal.
The signal from the external 24-MHz crystal is the source of the
CLK24M signal fed into USB PHY as the reference clock and to the
real time clock (RTC).
• Up to eight output sources multiplexed per pin
• Up to four destinations for each input pin
• Unselected input paths held at constant levels for reduced power
• Preprocessing of data from the sensor or from the external
• Postprocessing of data from the external system memory
• Post-filtering of data from the system memory with support of the
• Displaying video and graphics on a synchronous (dumb or
• Displaying video and graphics on an asynchronous (smart)
• Transferring data between IPU sub-modules and to/from the
consumption
system memory
MPEG-4 (both deblocking and deringing) and H.264 post-filtering
algorithms
memory-less) display
display
system memory with flexible pixel reformatting
2
Brief Description
C) is an industry-standard, bidirectional
Freescale Semiconductor
2
C is suitable for
2
C system is
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