MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 62

• Manufacturer Part Number: MCIMX35WPDKJ
• Description: BOARD DEV FOR I.MX35
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r
• Type: MPUr

Specifications of MCIMX35WPDKJ

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: i.MX35
• Processor Series: i.MX35
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, CAN, JTAG
• Core: ARM11
• For Use With/related Products: i.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.8.3
The transmitter timing signals consist of FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
1
Figure 41
4.9.8.4
The MII asynchronous timing signals are FEC_CRS and FEC_COL.
inputs signal timing.
1
62
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing when in 10 Mbps 7-wire interface mode.
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
Num
Num
M5
M6
M7
M8
M9
1
FEC_TXD[3:0] (outputs)
FEC_TX_CLK pulse width high
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER
valid
FEC_TX_CLK pulse width low
shows the MII transmit signal timings listed in
FEC_TX_CLK (input)
MII Transmit Signal Timing
MII Asynchronous Inputs Signal Timing
FEC_TX_EN
FEC_TX_ER
FEC_CRS to FEC_COL minimum pulse width
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Characteristic
Characteristic
Figure 41. MII Transmit Signal Timing Diagram
Table 47. MII Asynch Inputs Signal Timing
Table 46. MII Transmit Signal Timing
1
M5
Table 46
M6
M7
Table
lists MII transmit channel timings.
46.
Min.
35%
35%
Min.
1.5
—
5
Table 47
M8
Max.
Max.
65%
65%
20
—
—
lists MII asynchronous
FEC_TX_CLK period
FEC_TX_CLK period
FEC_TX_CLK period
Freescale Semiconductor
Unit
Unit
ns
ns