MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 73
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section 4.9.13.1.5, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics.”
images correspond to straight polarity of the Sharp signals.
Freescale Semiconductor
IP21
IP22
IP23
IP24
IP25
IP26
ID
DISPB_D3_DATA
DISPB_D3_SPL
DISPB_D3_CLS
DISPB_D3_REV
DISPB_D3_PS
DISPB_D3_CLK
DISPB_D3_HSYNC
SPL rise time
CLS rise time
CLS fall time
CLS rise and PS fall time
PS rise time
REV toggle time
Table 54. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
Figure 52. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Parameter
SPL pulse width is fixed and aligned to the first data of the line.
Example is drawn with FW + 1 = 320 pixel/line, FH + 1 = 240 lines.
REV toggles every HSYNC period.
IP24
IP22
Horizontal timing
IP21
IP23
Symbol
Tsplr
Tclsr
Tclsf
Tpsr
Tpsf
Trev
IP25
D1 D2
IP26
1 DISPB_D3_CLK period
(BGXP – 1) × Tdpcp
CLS_RISE_DELAY × Tdpcp
CLS_FALL_DELAY × Tdpcp
PS_FALL_DELAY × Tdpcp
PS_RISE_DELAY × Tdpcp
REV_TOGGLE_DELAY × Tdpcp
D320
Value
The timing
Units
ns
ns
ns
ns
ns
ns
73
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