MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 69
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4.9.13.1
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.
4.9.13.1.4
Figure 48
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
4.9.13.1.5
Figure 49
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
Freescale Semiconductor
•
•
•
•
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_HSYNC
DISPB_D3_DATA
DISPB_D3_DRDY
DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
DISPB_D3_HSYNC causes the panel to start a new line.
DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
DISPB_D3_CLK
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
Synchronous Interfaces
Interface to Active Matrix TFT LCD Panels, Functional Description
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n – 1
m – 1
LINE n
m
69
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