MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 144
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (3Mb)
6
All related product documentation for the i.MX35 processor is located at http://www.freescale.com/imx.
7
Table 95
between revision 1 and revision 4 or between revision 6 and revision 7.
144
Revision
W
R
U
Number
P
T
V
Y
_MDI
_TX_
DATA
9
8
7
ATA_
ATA_
GND
FEC
FEC
_MD
FEC
RTS
DA1
EN
14
O
C
1
1
1
Product Documentation
Revision History
_RX_
_RX_
INTR
DATA
DATA
ATA0
ATA_
ATA_
ATA_
FEC
_RD
FEC
FEC
RXD
CLK
shows the revision history of this document. Note: There were no revisions of this document
DV
13
11
12/18/2009 • Updated
Q
2
1
2
08/2010
04/2010
Date
DATA
DATA
DATA
DATA
ATA_
DMA
ATA_
ATA_
ATA_
ATA_
FEC
_CO
CTS
RQ
12
10
3
L
1
9
7
3
Table 94. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch (continued)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
_TX_
ATA_
ATA_
DATA
ATA_
DATA
ATA_
DATA
ATA_
DATA
ATA_
DATA
FEC
CLK
DA0
15
4
8
6
5
4
4
• Updated
• Updated
• Updated
_TDA
ATA_
ATA_
ATA_
DATA
ATA_
DATA
ATA_
DATA
ATA_
DATA
FEC
DA2
BUF
F_E
TA0
N
5
3
2
1
0
5
C_AT
ET_B
IORD
DIOR
ATA_
ATA_
ATA_
DMA
ATA_
ATA_
NVC
RES
TXD
DIO
CK
W
A
Y
6
1
6
Table 30, “NFC Timing Parameters.”
Table 31, “WEIM Bus Timing Parameters
Table
Table
Table 95. i.MX35 Data Sheet Revision History
C_AT
ATA_
ATA_
NVC
VDD
USB
OTG
_OC
USB
OTG
_PW
T_M
ODE
CS1
CS0
TES
A
R
7
3
7
14,
1,
“Ordering Information.”
“I/O Pin DC Electrical Characteristics.”
C_AT
CSPI
1_SP
CSPI
1_SS
EXT_
CSPI
1_SC
CSPI
1_SS
I_RD
ARM
NVC
VDD
CLK
LK
A
Y
8
3
1
0
8
CSPI
CSPI
POW
GND
BOO
ODE
1_MI
NVC
C_C
T_M
FAIL
VST
1_M
ER_
OSI
RM
SO
BY
9
1
9
CLK_
CLK_
MOD
MOD
GND
NVC
C_M
ET_I
BOO
ODE
RES
N_B
CLK
T_M
10
LB
E1
E0
10
O
0
Substantive Change(s)
GPIO
GPIO
GPIO
GPIO
MVD
NVC
POR
C_C
1_0
2_0
3_0
1_1
_B
11
11
SI
D
2_VS
SD2_
WDO
COM
DATA
_SIG
VDD
PHY
PAR
CAP
TUR
MLB
G_R
ST
12
12
S
4
E
3
E
2_VD
SD2_
DATA
SD2_
SD2_
DATA
_CLK
_DAT
CMD
PHY
MLB
MLB
FUS
E_V
DD
13
13
.”
D
1
0
SD1_
DATA
SD2_
SD2_
DATA
CSI_
CSI_
CSI_
NVC
VSY
HSY
C_S
CLK
DIO
D14
NC
NC
14
14
0
2
PIXC
CSI_
CSI_
CSI_
CSI_
CSI_
TDO
MCL
D11
D13
TDI
D8
LK
15
15
K
SD1_
C_JT
DATA
NVC
TMS
CSI_
CSI_
CSI_
TRS
D10
D12
D15
AG
16
TB
16
1
1_UP
SJC_
SD1_
LLVD
MOD
DATA
GND
CSI_
USB
PHY
TCK
USB
PHY
2_D
D9
17
17
Freescale Semiconductor
M
D
3
1_VB
1_VS
24M_
SD1_
SD1_
DATA
2_DP
BIAS
OSC
USB
PHY
USB
PHY
USB
PHY
SA_
VSS
RTC
CLK
US
18
18
K
2
1_DP
24M_
SD1_
DIO_
XTAL
CMD
USB
PHY
USB
PHY
OSC
VDD
OSC
REF
_AU
VSS
_AU
DE_
1_R
DIO
19
19
B
1_VD
EXTA
L24M
EXTA
1_VS
XTAL
L_AU
BIAS
OSC
DIO_
GND
PHY
USB
PHY
VDD
DA_
24M
_AU
DIO
SA
20
20
W
P
R
T
U
V
Y
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