MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 101

• Manufacturer Part Number: MCIMX35WPDKJ
• Description: BOARD DEV FOR I.MX35
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r
• Type: MPUr

Specifications of MCIMX35WPDKJ

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: i.MX35
• Processor Series: i.MX35
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, CAN, JTAG
• Core: ARM11
• For Use With/related Products: i.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ata_buffer_en is negated, the bus drives from device to host. Steering of the signal is such that contention
on the host and device tri-state buses is always avoided.
4.9.17.3
Table 65
implementation of the ATA interface on silicon, the bus buffer used, the cable delay, and the cable skew.
Freescale Semiconductor
tcable1 Cable propagation delay for ata_data
tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
tskew1 Maximum difference in propagation delay bus clock L-to-H to any of following signals
tskew2 Maximum difference in buffer propagation delay for any of following signals
tskew3 Maximum difference in buffer propagation delay for any of following signals ata_iordy,
tskew4 Maximum difference in cable propagation delay between ata_iordy and ata_data (read)
tskew5 Maximum difference in cable propagation delay between ( ata_dior, ata_diow, ata_dmack)
tskew6 Maximum difference in cable propagation delay without accounting for ground bounce
Name
ti_ds
ti_dh
tsui
tbuf
Values provided where applicable.
tco
tsu
thi
T
Bus clock period (ipg_clk_ata)
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Hold time ata_iordy edge to ata_data (UDMA-in only)
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
Set-up time ata_data to bus clock L-to-H
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
ata_data (read)
Maximum buffer propagation delay
and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
shows the parameters used in the timing equations. These parameters depend on the
Timing Parameters
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Table 65. ATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Contributing Factor
Peripheral clock
Transceiver
Transceiver
Transceiver
frequency
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
Cable
Cable
Cable
Cable
Cable
15 ns
10 ns
7 ns
5 ns
4 ns
7 ns
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