M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 117

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 5.4.6 Timer A2, A3, and A4 mode registers when two-phase pulse signal processing function is
Fig. 5.4.7 Normal processing
(2) Two-phase pulse signal processing function (Timers A2 to A4)
For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the two-
phase pulse signal processing select bits (bits 5 to 7 at address 44
Figure 5.4.6 shows the timer A2, A3, and A4 mode registers when the two-phase pulse signal
processing function is selected.
With timers selecting the two-phase pulse signal processing function, the timer counts two kinds of
pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal
processing: normal processing and quadruple processing. In timers A2 and A3, normal processing
is performed; in timer A4, quadruple processing is performed.
For some bits of the port P5 and P6 direction registers correspond to pins used for two-phase pulse
input, set these bits for the input mode.
Normal processing
The timer up-counts the rising edges to the TAk
TAk
is “H” level.
The timer down-counts the falling edges to the TAk
the TAk
(Refer to Figure 5.4.7.)
selected
IN
pin’s input signal level goes from “L” to “H” while the TAk
(k=2, 3)
IN
TAk
pin’s input signal level goes from “H” to “L” while the TAk
TAk
OUT
IN
b7
: It may be either “0” or “1.”
“H”
“L”
“H”
“L”
b6
b5
0
b4
1
count
count
+1
Up-
Up
b3
0 0 0 1
b2
7702/7703 Group User’s Manual
b1
count
+1
b0
Up-
Timer A2 mode register (Address 58
Timer A3 mode register (Address 59
Timer A4 mode register (Address 5A
+1
count
Up-
IN
pin when the phase has the relationship that the
IN
pin when the phase has the relationship that
Down-
count
–1
OUT
16
Down-
OUT
count
) to “1.” (Refer to Figure 5.4.5.)
(k = 2 and 3) pin’s input signal
–1
5.4 Event counter mode
pin’s input signal is “H” level.
16
16
16
)
)
)
Down-
count
–1
TIMER A
5–27