M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 82

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

register (PG), program counter (PC), and processor status register (PS) immediately before performing the
INTACK sequence, which were saved to the stack area, are automatically restored, and control returns to
the routine executed before the acceptance of interrupt request and processing is resumed from it left off.
same register length as it was saved by using the PUL instruction and others before executing the RTI
instruction.
has higher priority than the interrupt request being executed now by clearing the interrupt disable flag (I)
to “0” in the interrupt routine. This is multiple interrupts.
RTI instruction is executed, the interrupt priority level of the routine that the microcomputer was executing
before accepting the interrupt request is restored to the IPL. Therefore, one of the interrupt requests being
retained is accepted when the following condition is satisfied at next detection of interrupt priority level:
INTERRUPTS
4.8 Return from interrupt routine 4.9 Multiple interrupts
4.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
For any register that is saved by software in the interrupt routine, restore it with the same data length and
4.9 Multiple interrupts
When a branch is made to the interrupt routine, the microcomputer becomes the following situation:
Accordingly, as long as the IPL remains unchanged, the microcomputer can accept the interrupt request that
Figure 4.9.1 shows the multiple interrupt mechanism.
The interrupt requests that have not been accepted owing to their low priority levels are retained. When the
Interrupt priority level of interrupt request being retained > Restored processor interrupt priority level (IPL)
4–18
•Interrupt disable flag (I) = “1” (interrupts disabled)
•Interrupt request bit of the accepted interrupt = “0”
•Processor interrupt priority level (IPL) = interrupt priority level of the accepted interrupt
7702/7703 Group User’s Manual