M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 211

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 7.4.6 Example of transmit timing when transfer data length is 8 bits (when parity enabled,
Fig. 7.4.7 Example of transmit timing when transfer data length is 9 bits (when parity disabled,
interrupt request bit
Transmit enable bit
Transmit register
interrupt request bit
Transmit enable bit
Transmit buffer
UARTi transmit
Transfer clock
Transmit register
UARTi transmit
Transmit buffer
selecting 1 stop bit)
selecting 2 stop bits)
Transfer clock
empty flag
empty flag
empty flag
empty flag
CTS
T
TxD
ENDi
T
TxD
ENDi
i
i
The above timing diagram applies to
the following conditions:
The above timing diagram applies to
the following conditions:
“H”
“L”
Parity enabled
1 stop bit
CTS function selected
“1”
“0”
“1”
“0”
“1”
“0”
i
“1”
“0”
Parity disabled
2 stop bits
CTS function disabled
“1”
“0”
“0”
“0”
“0”
“1”
“1”
“1”
Start bit
ST
Cleared to “0” when interrupt request is accepted or cleared by software.
Start bit
ST
Cleared to “0” when interrupt request is accepted or cleared by software.
D
0
D
0
D
Data is set in UARTi transmit buffer register.
1
D
Tc
1
D
Data is set in UARTi transmit buffer register.
2
D
2
D
3
D
3
D
Tc
7702/7703 Group User’s Manual
4
D
4
D
5
T
(T
Tc: 16(n + 1)/fi or 16(n + 1)/f
D
ENDi
ENDi
T
(T
Tc: 16(n + 1)/fi or 16(n + 1)/f
5
D
7.4 Clock asynchronous serial I/O (UART) mode
ENDi
ENDi
6
D
Parity bit
: Next transmit conditions are examined when this signal level is “H.”
6
is an internal signal. Accordingly, it cannot be read from an external.)
D
: Next transmit conditions are examined when this signal level is “H.”
7
is an internal signal. Accordingly, it cannot be read from an external.)
f
D
EXT
7
f
EXT
P SP
fi: BRGi count source frequency (f
n: Value set to BRGi
UARTi transmit register
: BRGi count source frequency (external clock)
Stop bit
D
fi: BRGi count source frequency (f
n: Value set to BRGi
: BRGi count source frequency (external clock)
8
Stop bit
SP
UARTi transmit register
ST
SP
Stop bit
D
0
ST
EXT
D
EXT
1
D
0
D
2
D
1
D
3
D
2
UARTi transmit buffer register
D
Stopped because transmit enable bit = “0”
4
Stopped because transmit enable bit = “0”
D
2
, f
3
D
2
16
, f
5
UARTi transmit buffer register
D
16
, f
4
D
64
, f
6
, f
64
D
512
5
, f
D
512
7
)
D
6
)
P SP
D
7
D
8
SERIAL I/O
SP SP
ST
ST
D
0
D
0
D
1
D
1
7–45