M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 274

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CONNECTION WITH EXTERNAL DEVICES
12.1 Signals required for accessing external devices
Table 12.1.3 Levels of A
12–6
(2) External data bus width switching signal (BYTE pin level)
(3)
(4)
(5)
(6) Address latch enable signal (ALE)
(7)
(8)
Access address
level is “L,” the external data bus width is 16 bits; when the level is “H,” the bus width is 8 bits (refer
to Table 12.1.1.)
is always 16 bits.
Enable signal (E)
12.1.2.)
Read/Write signal (R/W)
bus. Table 12.1.2 lists the state of the data bus indicated with the E and R/W signals.
Byte high enable signal (BHE)
an only odd address or when simultaneously accessing odd and even addresses.
external data bus width is 16 bits.
This signal is used to select the external data bus width between 8 bits and 16 bits. When this signal
Fix this signal to either “H” or “L” level.
This signal is valid only for the external areas. When accessing the internal areas, the data bus width
This signal becomes “L” level while reading or writing data to and from the data bus. (See Table
This signal indicates the state of the data bus. This signal becomes “L” level while writing to the data
This signal indicates the access to an odd address. This signal becomes “L” level when accessing
This signal is used to connect memories or I/O devices of which data bus width is 8 bits when the
Table 12.1.3 lists levels of the external address bus A
Ready function-related signal (
Hold function-related signals (
This signal is used to obtain the address from the multiplexed signal of address and data that is input
and output to and from the A
is “H,” latch the address and simultaneously output the addresses. When this signal is “L,” retain the
latched address.
This is the signal to use the Ready function. (Refer to section “12.3 Ready function.”)
These are the signals to use the Hold function. (Refer to section “12.4 Hold function.”)
____
BHE
A
0
__
Even and odd addresses
(Simultaneous 2-byte access)
0
and BHE signal and access addresses
__
____
____
L
L
8
/D
8
HOLD
_____
to A
7702/7703 Group User’s Manual
____
RDY
15
)
,
/D
_____
HLDA
15
and A
)
Table 12.1.2 State of data bus indicated with E
16
(1-byte access)
/D
Even address
0
E
H
_
L
to A
0
H
L
and the
23
/D
7
and R/W signals
R/W
pins. Make sure that when this signal
H
H
L
L
__
____
BHE
__
_
signal and access addresses.
State of data bus
__
(1-byte access)
Odd address
Read data
Write data
Not used
H
L
_