M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 228

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A-D CONVERTER
8.2 Block description
Fig. 8.2.5 Structure of A-D conversion interrupt control register
8–8
8.2.4 A-D conversion interrupt control register
Figure 8.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts,
refer to “Chapter 4. INTERRUPTS.”
(1) Interrupt priority level select bits (bits 2 to 0)
(2) Interrupt request bit (bit 3)
b7
b6
select priority levels 1 to 7. When an A-D conversion interrupt request occurs, its priority level is
compared with the processor interrupt priority level (IPL) and the requested interrupt is enabled only
when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag
(I) = “0.”) To disable the A-D conversion interrupt, set these bits to “000
cleared to “0” when the A-D conversion interrupt request is accepted. This bit can be set to “1” or
cleared to “0” by software.
These bits select the A-D conversion interrupt’s priority level. When using A-D conversion interrupts,
This bit is set to “1” when an A-D conversion interrupt request occurs. This bit is automatically
b5
b4
b3
b2
b1
b0
A-D conversion interrupt control register (Address 70
7 to 4
Note : Use the SEB or CLB instruction to set the A-D conversion interrupt control register.
Bit
0
1
2
3
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
7702/7703 Group User’s Manual
Bit name
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
Functions
16
)
Low level
High level
2
” (level 0).
Undefined
At reset
0
0
0
0
RW
RW
RW
RW
RW
–