M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 230

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

contents of the successive approximation register, with the analog input voltage (V
the analog input pin (AN
is converted into a digital value. When a trigger is generated, the A-D converter performs the following
processing:
register. Table 8.3.1 lists the relationship between the successive approximation register’s contents and V
Table 8.3.2 lists changes of the successive approximation register and V
8.3.1 shows the ideal A-D conversion characteristics.
A-D CONVERTER
8.3 A-D conversion method
8.3 A-D conversion method
The A-D converter compares the comparison voltage (V
The comparison voltage (V
Table 8.3.1 Relationship between successive approximation register’s contents and V
V
8–10
REF
Successive approximation register’s contents: n
: Reference voltage
Determining bit 7 of the successive approximation register
register is “10000000
Determining bit 6 of the successive approximation register
with V
Determining bits 5 to 0 of the successive approximation register
is transferred to the A-D register i.
The A-D converter compares V
Bit 7 of the successive approximation register changes according to the comparison result as follows:
When V
When V
After setting bit 6 of the successive approximation register to “1,” the A-D converter compares V
When V
When V
Operations in
When bit 0 is determined, the contents (conversion result) of the successive approximation register
IN
. Bit 6 changes according to the comparison result as follows:
ref
ref
ref
ref
< V
> V
< V
> V
IN
IN
IN
IN
1 to 255
, bit 7 = “1”
, bit 7 = “0”
, bit 6 = “1”
, bit 6 = “0”
are performed for bits 5 to 0.
i
). By reflecting the comparison result on the successive approximation register, V
0
ref
) is generated according to the latest contents of the successive approximation
2
” (initial value).
ref
with V
7702/7703 Group User’s Manual
IN
. At this time, the contents of the successive approximation
ref
), which is internally generated according to the
V
256
ref
REF
during the A-D conversion. Figure
V
ref
0
(V)
(n – 0.5)
IN
), which is input from
ref
ref
ref
IN
.