M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 336

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

according to the actual application and test them.
EXTERNAL DEVICES” for details about the functions and operation of used pins when expanding a memory
or I/O. Refer to “Chapter 15. ELECTRICAL CHARACTERISTICS” for timing requirements of the microcomputer.
voltage version.
APPLICATION
17.1 Memory expansion
This chapter describes application. Application shown here is just an example. The user shall modify them
17.1 Memory expansion
This section shows examples for memory and I/O expansion. Refer to “Chapter 12. CONNECTION WITH
Refer to “Chapter 18. LOW VOLTAGE VERSION” for timing requirements and application of the low
17–2
17.1.1 Memory expansion model
Memory expansion to the external is possible in the memory expansion mode or the microprocessor mode.
The level of the external data bus width select signal makes it possible to select the four memory expansion
models shown in Table 17.1.1.
(1) Minimum model
(2) Medium model A
(3) Medium model B
(4) Maximum model
expanded up to 64 Kbytes. It is unnecessary to connect the address latch externally. This is an
expansion model having the cost priority which is suited for connecting the memory of which external
data bus width is 8 bits.
expanded up to 16 Mbytes. In this expansion model, the high-order 8 bits of the external address bus
(A
required for latching addresses (n bits of A
expanded up to 64 Kbytes. This expansion model is used when having the speed performance
priority. In this expansion model, the middle-order 8 bits of the external address bus (A
multiplexed with the external data bus. Accordingly, an 8-bit address latch is required for latching
address (A
expanded up to 16 Mbytes. In this expansion model, the high- and middle-order 16 bits of the
external address bus (A
address latch for latching A
are required.
This is an expansion model of which external data bus width is 8 bits and accessible area is
This is an expansion model of which external data bus width is 8 bits and accessible area is
This is an expansion model of which external data bus width is 16 bits and accessible area is
This is an expansion model of which external data bus width is 16 bits and accessible area is
23
to A
16
) are multiplexed with the external data bus. Accordingly, an n-bit (n
15
to A
8
).
23
to A
15
to A
8
) are multiplexed with the external data bus. Accordingly, an 8-bit
7702/7703 Group User’s Manual
8
and an n-bit (n
23
to A
16
).
8) address latch for latching n bits of A
8) address latch is
15
to A
23
8
to A
) are
16