M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 173
M37702E6BFS
Manufacturer Part Number
M37702E6BFS
Description
EPROM MCU/8BIT CMOS EMULATION CH
Manufacturer
Renesas Electronics America
Datasheet
1.M37702E6BFS.pdf
(524 pages)
Specifications of M37702E6BFS
Accessory Type
Emulator EPROM MCU
For Use With/related Products
7702
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M37702E6BFS
Manufacturer:
MITSUBISHI/三菱
Quantity:
20 000
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Fig. 7.2.4 Structure of UARTi transmit/receive control register 1
7.2.3 UARTi transmit/receive control register 1
Figure 7.2.4 shows the structure of UARTi transmit/receive control register 1. For bits 4 to 7, refer to each
operation mode’s description.
b7
b6
b5
b4
b3
b2
b1
b0
UART0 transmit/receive control register 1 (Address 35
UART1 transmit/receive control register 1 (Address 3D
Notes 1: Bits 7 to 4 are cleared to “0” when clearing the receive enable bit to “0” or when reading
Bit
0
6
7
1
4
5
2
3
2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode.
Transmit enable bit
Parity error flag
Error sum flag
Transmit buffer empty flag
Overrun error flag
Framing error flag
Receive enable bit
Receive complete flag
(Valid in UART mode)
(Valid in UART mode)
(Valid in UART mode)
the low-order byte of the UARTi receive buffer register (addresses 36
7702/7703 Group User’s Manual
Bit name
(Notes 1, 2)
(Notes 1, 2)
(Notes 1, 2)
(Note 1)
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in transmit buffer
1 : No data present in transmit
0 : No overrun error
1 : Overrun error detected
0 : No framing error
1 : Framing error detected
0 : No parity error
1 : Parity error detected
0 : Reception disabled
1 : Reception enabled
0 : No data present in receive
1 : Data present in receive buffer
0 : No error
1 : Error detected
register.
buffer register.
buffer register.
register.
Functions
16
16
)
)
7.2 Block description
SERIAL I/O
16
, 3E
At reset
16
0
0
0
0
1
0
0
0
) out.
RW
RW
RW
RO
RO
RO
RO
RO
RO
7–7
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