M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 71

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 4.3.2 Structure of interrupt control register
b7
b7
b6
b6
b5
b5
b4
b4
b3
b3
b2
b2
b1
b1
b0
b0
INT
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2
interrupt control registers (Addresses 70
Notes 1: The INT
Note: Use the SEB or CLB instruction to set each interrupt control register.
7 to 4
0
7, 6
Bit
Bit
to INT
0
1
2
3
0
1
2
3
4
5
2: Use the SEB or the CLB instruction to set the INT
Interrupt priority level select bits
Interrupt request bit
Nothing is allocated.
Interrupt priority level select bits
Polarity select bit
Level sense/Edge sense select
bit
Nothing is allocated.
Interrupt request bit (Note 1)
2
interrupt control registers (Addresses 7D
7702/7703 Group User’s Manual
0
to INT
Bit name
Bit name
2
interrupt request bits are invalid when selecting the level sense.
16
to 7C
16
b2 b1 b0
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
0 : Edge sense
1 : Level sense
)
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : No interrupt request
1 : Interrupt request
0 : Set the interrupt request bit at
1 : Set the interrupt request bit at
“H” level for level sense and at
falling edge for edge sense.
“L” level for level sense and at
rising edge for edge sense.
Functions
Functions
16
to 7F
0
to INT
Low level
High level
Low level
High level
16
INTERRUPTS
)
4.3 Interrupt control
2
interrupt control registers.
At reset
Undefined
At reset
Undefined
0
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
–
–
4–7