M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 260

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 10.2.2 Interrupts used to terminate Stop mode
Notes 1: Since the oscillator has stopped oscillating, each function does not work unless they are operated
STOP MODE
10.2 Operation description
____
10–4
INT
Timer Ai interrupt (i = 0 to 4)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
10.2.1 Termination by interrupt request occurrence
When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time
measured by the watchdog timer has passed.
Table 10.2.2 lists the interrupts used to terminate Stop mode.
Before executing the STP instruction, enable interrupts used to terminate Stop mode.
In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the
processor interrupt priority level (IPL) of the routine where the STP instruction is executed. When multiple
interrupts in Table 10.2.2 are enabled, Stop mode is terminated by the first interrupt request.
There is possibility that all interrupt requests occur after the oscillation starts in
and
(Note) after the watchdog timer’s MSB becomes “0.”
For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before
executing the STP instruction.
Note : The interrupt request which has the highest priority is accepted first.
When the watchdog timer’s MSB becomes “0,” supply of
i
When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of clock
The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts f
The interrupt request which occurs in
to f
timer’s count source returns to f
0 at address 61
interrupt (i = 0 to 2)
2: Since the oscillator has stopped oscillating, no interrupts other than those above can be used.
3: Refer to “Chapter 4. INTERRUPT” and the description of each internal peripheral device for
BIU
512
under the above condition. Also, the A-D converter does not work.
details about each interrupt.
starts in
starts.
Interrupt
16
. The interrupt requests which occur during this time are accepted in order of priority
).
32
or f
7702/7703 Group User’s Manual
Enabled in event counter mode
Enabled when selecting external clock
Conditions for using each function to generate interrupt request
512
that is selected by the watchdog timer frequency select bit (bit
is accepted.
CPU
,
BIU
starts. At the same time, the watchdog
and until supply of
32
.
1
, f
CPU
2