M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 72

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

INTERRUPTS
4.3 Interrupt control
4–8
4.3.1 Interrupt disable flag (I)
All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts
are disabled; when the flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1”
at reset, clear the flag to “0” when enabling interrupts.
4.3.2 Interrupt request bit
When an interrupt request occurs, this bit is set to “1.” The bit remains set to “1” until the interrupt request
is accepted, and it is cleared to “0” when the interrupt request is accepted.
This bit also can be set to “0” or “1” by software. Use the SEB or CLB instruction to set this bit.
For the INT
ignored.
4.3.3 Interrupt priority level select bits and processor interrupt priority level (IPL)
The interrupt priority level select bits are used to determine the priority level of each interrupt. Use the SEB
or CLB instruction to set these bits.
When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority
level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition.
Accordingly, an interrupt can be disabled by setting its interrupt priority level to 0.
Table 4.3.1 lists the setting of interrupt priority level, and Table 4.3.2 lists the interrupt enabled level
corresponding to IPL contents.
All the interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor
interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt
requests are accepted only when the following conditions are satisfied.
•Interrupt disable flag (I) = “0”
•Interrupt request bit = “1”
•Interrupt priority level > Processor interrupt priority level (IPL)
____
Each interrupt priority level > Processor interrupt priority level (IPL)
i
interrupt request bit (i = 0 to 2), when using the INT
7702/7703 Group User’s Manual
____
i
interrupt with level sense, the bit is