M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 37

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(6) Bit 5: Data length flag (m)
(7) Bit 6: Overflow flag (V)
(8) Bit 7: Negative flag (N)
(9) Bits 10 to 8: Processor interrupt priority level (IPL)
Note: When transferring data between registers which are different in bit length, the data is transferred
It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16-
bit unit when this flag is “0,” and as an 8-bit unit when it is “1.”
Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear
it to “0.” This flag is cleared to “0” at reset.
It is used when adding or subtracting with a word regarded as signed binary. When the data length
flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the
range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag
(m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range
between –128 and +127, and cleared to “0” in all other cases.
The overflow flag is also set to “1” when a result of division exceeds the register length to be stored
in the DIV instruction, a division instruction.
When the BVC or BVS instruction is executed, this flag’s contents determine whether the program
causes a branch or not.
Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result
is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m)
is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag
determines whether the program causes a branch or not. Use the SEP instruction to set this flag to
“1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode.
These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The
interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each
interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in
the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request.
There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the
new IPL into the stack area and updating the processor status register with the PUL or PLP instruction.
The contents of IPL is cleared to “000
with the length of the destination register, but except for the TXA, TYA, TXB, TYB and TXS
instructions. Refer to “7700 Family Software Manual” for details.
CENTRAL PROCESSING UNIT (CPU)
7702/7703 Group User’s Manual
2
” at reset.
2.1 Central processing unit
2–9