M37702E6BFS Renesas Electronics America, M37702E6BFS Datasheet - Page 36

• Manufacturer Part Number: M37702E6BFS
• Description: EPROM MCU/8BIT CMOS EMULATION CH
• Manufacturer: Renesas Electronics America

Specifications of M37702E6BFS

• Accessory Type: Emulator EPROM MCU
• For Use With/related Products: 7702
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 2.1.5 Processor status register structure
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit
2–8
2.1.9 Processor status register (PS)
The processor status register is an 11-bit register.
Figure 2.1.5 shows the structure of the processor status register.
(1) Bit 0: Carry flag (C)
(2) Bit 1: Zero flag (Z)
(3) Bit 2: Interrupt disable flag (I)
(4) Bit 3: Decimal mode flag (D)
(5) Bit 4: Index register length flag (x)
Note: “0” is always read from each of bits 15–11.
Note: When transferring data between registers which are different in bit length, the data is transferred
operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction
is executed, this flag’s contents determine whether the program causes a branch or not.
it to “0.”
otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the
program causes a branch or not.
zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted,
this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set
this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset.
is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with each word
treated as two or four digits decimal (determined by the data length flag). Decimal adjust is automatically
performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP
instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared
to “0” at reset.
an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit
register when it is “1.” Use the SEP instruction to set this flag to “1,” and use the CLP instruction
to clear it to “0.” This flag is cleared to “0” at reset.
It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic
Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear
It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when
Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.”
Note: This flag is invalid in the decimal mode addition (the ADC instruction).
It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and
It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic
It determines whether each of index register X and index register Y is used as a 16-bit register or
b15
0
b14
with the length of the destination register, but except for the TXA, TYA, TXB, TYB and TXS
instructions. Refer to “7700 Family Software Manual” for details.
0
b13
0
b12
0
b11
0
b10
b9
IPL
7702/7703 Group User’s Manual
b8
b7
N
b6
V
b5
m
b4
x
b3
D
b2
I
b1
Z
b0
C
Processor staus
register (PS)