MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 272

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15.4.11 Interrupt Mask Registers (UIMRn)
The UIMR registers select the corresponding bits in the UISR that cause an interrupt. By setting the bit,
the interrupt is enabled. If one of the bits in the UISR is set and the corresponding bit in the UIMR is also
set, the internal interrupt output is asserted. If the corresponding bit in the UIMR is zero, the state of the
bit in the UISR has no effect on the interrupt output. The UIMR does not mask the reading of the UISR.
15-26
RxRDY
TxRDY
Field
Address MBAR + $1D4 (UIMR0)
COS
6–3
DB
7
2
1
0
Reset
Field
COS
6–3
DB
W
7
2
R
Change-of-State
1 A change-of-state has occurred at the CTS input and has been selected to cause an interrupt by programming bit
0 COS bit in the UIPCR is not selected.
Reserved
Delta Break
1 The receiver has detected the beginning or end of a received break.
0 No new break-change condition to report. Refer to
Receiver Ready or FIFO Full
UMR1 bit 6 programs the function of this bit. It is a duplicate of either the FFULL or RxRDY bit of USR.
Transmitter Ready
This bit is the duplication of the TxRDY bit in USR.
1 The transmitter holding register is empty and ready to be loaded with a character.
0 The CPU loads the transmitter-holding register or the transmitter is disabled. Characters loaded into the
MBAR + $214 (UIMR1)
MBAR2 + $C14 (UIMR2)
transmitter-holding register when TxRDY=0 are not transmitted.
0 of the UACR.
information on the reset break-change interrupt command.
COS
0
7
Change-of-State
1 Enable interrupt
0 Disable interrupt
Reserved
Delta Break
1 Enable interrupt
0 Disable interrupt
Table 15-16. Interrupt Status Register (UISRn) Field Descriptions
Table 15-17. Interrupt Mask Register (UIMRn) Field Descriptions
0
6
Figure 15-18. Interrupt Mask Register (UIMRn)
MCF5253 Reference Manual, Rev. 1
0
5
0
4
Description
Section 15.4.5, “Command Registers (UCRn),”
Description
0
3
DB
0
2
FFULL
Freescale Semiconductor
Access: User write only
0
1
for more
TXRDY
0
0