MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 582

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.9.14.1.4 USB Interrupt (Interrupt on Completion (IOC))
Transfer Descriptors (iTDs, siTDs, and queue heads (qTDs)) contain a bit that can be set to cause an
interrupt on their completion. The completion of the transfer associated with that schedule item causes the
USB Interrupt (USBINT) bit in the USBSTS register to be set. In addition, if a short packet is encountered
on an IN transaction associated with a queue head, then this event also causes USBINT to be set. If the
USB Interrupt Enable bit in the USBINTR register is set, a hardware interrupt is signaled to the system at
the next interrupt threshold. If the completion is because of errors, the USBERRINT bit in the USBSTS
register is also set.
24.9.14.1.5 Short Packet
Reception of a data packet that is less than the endpoint's Max Packet size during Control, Bulk or Interrupt
transfers signals the completion of the transfer. Whenever a short packet completion occurs during a queue
head execution, the USBINT bit in the USBSTS register is set. If the USB Interrupt Enable bit is set in the
USBINTR register, a hardware interrupt is signaled to the system at the next interrupt threshold.
24.9.14.2 Host Controller Event Interrupts
These interrupt sources are independent of the interrupt threshold (with the one exception being the
Interrupt on Async Advance.
24.9.14.2.1 Port Change Events
Port registers contain status and status change bits. When the status change bits are set, the host controller
sets the Port Change Detect bit in the USBSTS register. If the Port Change Interrupt Enable bit in the
USBINTR register is set, then the host controller issues a hardware interrupt. The port status change bits
include:
24.9.14.2.2 Frame List Rollover
This event indicates that the host controller has wrapped the frame list. The current programmed size of
the frame list effects how often this interrupt occurs. If the frame list size is 1024, then the interrupt occurs
every 1024 milliseconds, if it is 512, then it occurs every 512 milliseconds, etc. When a frame list rollover
is detected, the host controller sets the Frame List Rollover bit in the USBSTS register. If the Frame List
Rollover Enable bit in the USBINTR register is set, the host controller issues a hardware interrupt. This
interrupt is not delayed to the next interrupt threshold.
24.9.14.2.3 Interrupt on Async Advance
This event is used for deterministic removal of queue heads from the asynchronous schedule. Whenever
the host controller advances the on-chip context of the asynchronous schedule, it evaluates the value of the
Interrupt on Async Advance Doorbell bit in the USBCMD register. If it is set, it sets the Interrupt on Async
24-120
•
•
•
•
Connect Status Change
Port Enable/Disable Change
Over-current Change
Force Port Resume
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor