MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 377

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

20.3.1
Although many BDM operations can occur in parallel with CPU operation, unrestricted BDM operation
requires the CPU to be halted. A number of sources can cause the CPU to halt, including the following as
shown in order of priority:
There are two special cases involving the assertion of the BKPT pin to be considered.
After the system reset signal is negated, the processor waits for 16 clock cycles before beginning reset
exception processing. If the BKPT input pin is asserted within the first eight cycles after RSTI is negated,
the processor enters the halt state, signaling that halt status, ($F), on the PST outputs. While in this state,
all resources accessible through the debug module can be referenced. This is the only opportunity to force
the ColdFire processor into emulation mode using the EMU bit in the configuration/status register (CSR).
Once the system initialization is complete, the processor response to a BDM GO command is dependent
on the set of BDM commands performed while breakpointed. Specifically, if the processor’s PC register
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1. The occurrence of the catastrophic fault-on-fault condition automatically halts the processor.
2. The occurrence of a hardware breakpoint can be configured to generate a pending halt condition in
3. The execution of the HALT ColdFire instruction immediately suspends execution. By default this
4. The assertion of the BKPT input pin is treated as a pseudo-interrupt. For example, the halt
The read/write control register commands, RCREG and WCREG use the register coding scheme
from the MOVEC instruction.
The read/write debug module register commands, RDMREG and WDMREG support debug
module register accesses.
Illegal command responses can be returned using the FILL and DUMP commands, if not
immediately preceded by certain, specific BDM commands.
For any command performing a byte-sized memory read operation, the upper 8 bits of the response
data are undefined. The referenced data is returned in the lower 8 bits of the response.
The debug module forces alignment for memory-referencing operations: long accesses are forced
to a 0-modulo-4 address; word accesses are forced to a 0-modulo-2 address. An address error
response is never returned.
a manner similar to the assertion of the BKPT signal. In all cases, the assertion of this type of halt
is first made pending in the processor. Next, the processor samples for pending halt and interrupt
conditions once per instruction. Once the pending condition is asserted, the processor halts
execution at the next sample point. See
is a supervisor instruction and attempted execution while in user mode generates a privilege
violation exception. A User Halt Enable (UHE) control bit is provided in the Configuration/Status
Register (CSR) to allow execution of HALT in user mode. The processor may be restarted after the
execution of the HALT instruction by serial shifting a “GO” command into the debug module.
Execution continues at the instruction following the HALT opcode.
condition is made pending until the processor core samples for halts/interrupts. The processor
samples for these conditions once during the execution of each instruction. If there is a pending
halt condition at the sample time, the processor suspends execution and enters the halted state.
CPU Halt
MCF5253 Reference Manual, Rev. 1
Section 20.4.1, “Theory of Operation,”
Background Debug Mode (BDM) Interface
for more detail.
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