MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 486

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.6.3.7
This register is not defined in the EHCI specification. The upper seven bits of this register represent the
device address. After any controller reset or a USB reset, the device address is set to the default address
(0). The default address will match all incoming addresses. The software shall reprogram the address after
receiving a SET_ADDRESS descriptor.
This register is shared between the host and device mode functions. In device mode, it is the
DEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See
“Periodic Frame List Base Address Register (PERIODICLISTBASE),”
24.6.3.8
This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.
Bits [4–0] of this register cannot be modified by the system software and always return zeros when read.
Note that on the USB OTG module, this register is shared between the host and device mode functions. In
host mode, it is the ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDR
register. See
for more information.
24-24
Address MBAR2 0x754 (Device Mode)
Reset
Reset
USBADR
W
W
31–25
R
R
Field
24–0
31
15
0
0
Section 24.6.3.9, “Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI,”
Device Address Register (DEVICEADDR), Non-EHCI
Current Asynchronous List Address Register (ASYNCLISTADDR)
Device Address. This field corresponds to the USB device address.
Reserved.
30
14
0
0
Table 24-21. Device Address (DEVICEADDR) Register Field Descriptions
29
13
0
0
USBADR
Figure 24-19. Device Address (DEVICEADDR) Register
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Description
24
0
0
8
23
0
0
7
22
0
0
6
21
0
0
5
for more information.
20
0
0
4
19
0
0
3
Freescale Semiconductor
Section 24.6.3.6,
Access: User read/write
18
0
0
2
17
0
0
1
16
0
0
0