MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 630

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

FlexCAN Module
25.5.6
ERRSTAT n reflects various error conditions, some general status of the device, and is the source of three
interrupts to the CPU. The reported error conditions (bits 15:10) are those occurred since the last time the
CPU read this register. The read action clears bits 15-10. Bits 9–3 are status bits.
Most bits in this register are read only, except for BOFFINT, WAKINT, and ERRINT, which are interrupt
flags that can be cleared by writing 1 to them. Writing 0 has no effect. Refer to
25-14
RXECTR
TXECTR
Offset MBAR2 0x1020 (CANCTRL0)
Reset
Reset
31–16
Field
15–8
Offset MBAR2 0x101C (ERRCNT0)
Reset 0
7–0
•
W
W
R
R BIT1
W
R 0
If the RXECTR increases to a value greater than 127, it is not incremented further, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127 to resume to error-active state.
MBAR2 0x2020 (CANCTRL1)
ERR
MBAR2 0x201C (ERRCNT1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31
15
0
0
0
Reserved, should be cleared.
Receive error counter. Indicates current number of receive errors.
Transmit error counter. Indicates current number of transmit errors.
FlexCAN Error and Status Register (ERRSTATn)
0
0
BIT0
ERR
30
14
0
0
Table 25-7. FlexCAN Error Counter (ERRCNTn) Register Field Descriptions
0
0
0
0
0
ACK
ERR
29
13
0
0
0
0
0
Figure 25-9. FlexCAN Error and Status (ERRSTATn) Register
Figure 25-8. FlexCAN Error Counter (ERRCNTn) Register
0
0
CRC
ERR
28
12
0
0
0
0
0
0
0
FRM
ERR
27
11
0
0
0
0
0
0
0
MCF5253 Reference Manual, Rev. 1
ERR
STF
26
10
0
0
0
0
0
0
0
WRN
TX
25
0
0
0
9
0 0
0
0
WRN
RX
24
0
0
0
8
0
0
Description
0
0
IDLE TXRX
23
0
0
0
7
0
0
22
0
0
0
0
6
RXECTR
0
0
21
0
0
0
5
CONF
FLT
0
0
9
20
0
0
0
4
Section 25.7.1, “Interrupts.”
0
8
0
7
19
0
0
0
0
3
Freescale Semiconductor
Access: User read/write
0
6
Access: User read/write
BOFF
INT
5
0
18
0
0
0
2
TXECTR
0
4
ERR
0
3
INT
17
0
0
0
1
0
2
0
1
16
0
0
0
0
0
0
0