MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 524

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.8.6.1
The first DWord of a Queue Head contains a link pointer to the next data object to be processed after any
required processing in this queue has been completed, as well as the control bits defined below.
This pointer may reference a queue head or one of the isochronous transfer descriptors. It must not
reference a queue element transfer descriptor.
24.8.6.2
The second and third DWords of a Queue Head specifies static information about the endpoint. This
information does not change over the lifetime of the endpoint. There are three types of information in this
region:
The host controller must not modify the bits in this region.
24-62
31–5 QHLP Queue Head Horizontal Link Pointer. This field contains the address of the next data object to be processed in
4–3
2–1
Bit
0
•
•
•
Name
Typ
Endpoint Characteristics. These are the USB endpoint characteristics including addressing,
maximum packet size, and endpoint speed.
Endpoint Capabilities. These are adjustable parameters of the endpoint. They effect how the
endpoint data stream is managed by the host controller.
Split Transaction Characteristics. This data structure is used to manage full- and low-speed data
streams for bulk, control, and interrupt via split transactions to USB2.0 Hub Transaction
Translator. There are additional fields used for addressing the hub and scheduling the protocol
transactions (for periodic).
–
T
the horizontal list and corresponds to memory address signals [31–5], respectively.
Reserved. These bits must be written as zeros.
This field indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This
allows the host controller to perform the proper type of processing on the item after it is fetched.
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate.
1 Last QH (pointer is invalid).
0 Pointer is valid.
If the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that this
is the end of the periodic list. This bit is ignored by the host controller when the queue head is in the
Asynchronous schedule. The software must ensure that queue heads reachable by the host controller always
have valid horizontal link pointers.
Queue Head Horizontal Link Pointer
Endpoint Capabilities/Characteristics
Table 24-55. Queue Head DWord 0
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor